1. Field of the Invention
The present invention relates to a gain control amplifier, and more particularly, to a gain control amplifier outputting a voltage from which a direct current (DC) offset component has been removed.
2. Description of the Related Art
In general, an operational amplifier (hereinafter, referred to as an OP AMP) used in a gain control amplifier includes an input offset voltage caused by mismatching occurring in a fabricating process. Thus, a voltage output from the gain control amplifier includes an undesired DC offset component. Therefore, a compensation must be performed with respect to the undesired DC offset component to obtain an output voltage a user desires to obtain.
FIG. 1 is a circuit diagram illustrating an example of a conventional gain control amplifier. Referring to FIG. 1, a gain control amplifier 100 includes first and second inverting amplifiers 110 and 120. The first inverting amplifier 110 has a structure in which a plurality of feedback resistors 2R, 4R, 6R, and 8R are connected to one another in parallel between a non-inverting terminal and an output terminal of an OP AMP 111, and a plurality of switches S0, S1, S2, and S3 are respectively connected to the plurality of feedback resistors 2R, 4R, 6R, and 8R in series. Only one of the plurality of switches S0, S1, S2, and S3 is turned on and the others are turned off according to a 2-bit digital control signal input via a 2-to-4 decoder (not shown) so that only one of the plurality of feedback resistors 2R, 4R, 6R, and 8R selectively connects the non-inverting and output terminals of the OP AMP 111. Thus, the first inverting amplifier 110 inversely amplifies an alternating component of an input signal Vi using one of voltage gains 2, 4, 6, and 8 based on a DC reference voltage Vcnt to output a voltage Vo1.
If the voltage Vo1 output from the first inverting amplifier 110 is applied to an inverting terminal of an OP AMP 121 of the second inverting amplifier 120 and the DC reference voltage Vcnt is applied to a non-inverting terminal of the OP AMP 121, a resistance value of a resistor RinV receiving the voltage Vo1 and applying the voltage Vo1 to the inverting terminal of the OP AMP 121 is equal to a resistance value of a resistor Rinv connecting the inverting and output terminals of the OP AMP 121. Thus, the second inverting amplifier 120 re-inverts and outputs the voltage Vo1 without a voltage gain. As a result, the gain control amplifier 100 non-inverting amplifies the alternating component of the input signal Vi using one of the voltage gains 2, 4, 6, and 8 based on the DC reference voltage Vcnt to output a voltage Vo2. Voltage powers Vos connected to the non-inverting terminals of the OP AMPs 111 and 121 indicate an input offset voltage of the OP AMPs 111 and 121. Thus, hereafter, a voltage power Vos connected to a non-inverting terminal of each OP AMP indicates an input offset voltage of OP AMPs. Here, it is supposed that offsets of adjacent OP AMPs in a chip have almost similar characteristics and thus have the same magnitude.
FIGS. 2A through 2C illustrate a relationship between the voltage Vi input to the first inverting amplifier 110 and the voltage Vo1 output from the first inverting amplifier 110 when the DC reference voltage Vcnt is 1.65V and the input offset voltage Vos is 20 mV, 0 mV, or −20 mV. Here, bold lines denote the input voltage Vi, and slender lines denote the output voltage Vo1 generated by inverting amplifying the alternating component of the input voltage Vi using one of the voltage gains 2, 4, 6, and 8. In a case where the input offset voltage Vos of the OP AMPs 111 and 121 is 0 mV, the output voltage Vo1 does not include a DC offset component as shown in FIG. 2B. In a case where the input offset voltage Vos is 20 mV or −20 mV, the output voltage Vo1 includes an undesired DC offset component as shown in FIGS. 2A and 2C.
FIG. 3 is a graph illustrating DC levels of the output voltage Vo1 of the first inverting amplifier 110. Here, a horizontal axis denotes a voltage gain, and a vertical axis denotes DC levels of the output voltage Vo1. In a case where the input offset voltage Vos is 0 mV, a DC level of the output voltage Vo1 is kept at 1.65V that is the DC reference voltage. In a case where the input offset voltage Vos is 20 mV, the DC level of the output voltage Vo1 is gradually increased with an increase of the voltage gain. In a case where the input offset voltage Vos is −20 mV, the DC level of the output voltage Vo1 is gradually decreased with the increase of the voltage gain. In other words, an effect of the undesired DC offset component on the output voltage Vo1 is increased with the increase of the voltage gain.
FIG. 4 is a circuit diagram of a gain control amplifier in which an effect of a DC offset component has been improved by inserting an OP AMP 112 into the first inverting amplifier 110 shown in FIG. 1 in the form of voltage follower. If the OP AMP 112 is inserted in the form of a voltage follower as shown in FIG. 4, the input offset voltage Vos of the OP AMP 111 is offset by an input offset voltage Vos of the OP AMP 112. Thus, the DC offset component is removed from the output voltage Vo1.
FIGS. 5A and 5B are graphs respectively illustrating DC levels of the output voltages Vo1 and Vo2 of the first and second inverting amplifiers 110 and 120 shown in FIG. 4. Referring to FIGS. 5A and 5B, horizontal axes denote a voltage gain, and vertical axes respectively denote DC levels of the output voltages Vo1 and Vo2.
As shown in FIG. 5A, the DC level of the output voltage Vo1 of the first inverting amplifier 110 is 1.65V and thus does not include the DC offset component due to the OP AMP 112 inserted in the form of voltage follower. However, the output voltage Vo2 of the second inverting amplifier 120 still includes a DC offset component as shown in FIG. 5B.
Accordingly, the DC offset component is not completely removed from the conventional gain control amplifier 100. Also, an OP AMP must be additionally used in the form of voltage follower to remove a DC offset component from the second inverting amplifier 120. Thus, the area of a chip is increased, and power consumption is increased.
In addition, in a case where a voltage gain is controlled at 2N stages using an N-bit digital control signal, the conventional gain control amplifier 100 requires an N-to-2N decoder and 2N feedback resistors.